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Final Year IEEE VLSI Project Titles – 2015

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CODE PROJECT TITLE
1CP_VLSI_001 A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT
1CP_VLSI_002 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
1CP_VLSI_003 A High-Speed FPGA Implementation of an RSD-Based ECC Processor
1CP_VLSI_004 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
1CP_VLSI_005 An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability
1CP_VLSI_006 An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
1CP_VLSI_007 An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC
1CP_VLSI_008 Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design
1CP_VLSI_009 Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
1CP_VLSI_010 Exact and Approximate Algorithms for the Filter Design Optimization Problem
1CP_VLSI_011 Fault Tolerant Parallel Filters Based on Error Correction Codes
1CP_VLSI_012 Graph-Based Transistor Network Generation Method for Supergate Design
1CP_VLSI_013 High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
1CP_VLSI_014 Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
1CP_VLSI_015 Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System
1CP_VLSI_016 Optimal Factoring of FIR Filters
1CP_VLSI_017 Recursive Approach to the Design of a Parallel Self-Timed Adder
1CP_VLSI_018 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
1CP_VLSI_019 Reverse Converter Design via Parallel-Prefix Adders: Novel Components,Methodology, and Implementations